In the technology with a critical dimension of 65 nm or less, it is generally required that a poly-silicon gate in the device should be composed of N-doped poly-silicon and undoped poly-silicon. Due to the effect of N-type ion doping, the etching rate of the N-doped poly-silicon is larger than that of the undoped poly-silicon.
In an automatic end point detection system, the basis for determining the termination of the poly-silicon gate etching is that both the N-doped and undoped poly-silicon gates are completely etched. In case that the etching of the N-doped poly-silicon gate is completed in advance due to its relatively larger etching rate, and the plasma bombardment is still performed in order to etch the undoped poly-silicon gate, the bottom of the N-doped poly-silicon gate will be damaged, thus developing an under-cut. In this process condition, there will be a difference between the N-type and P-type semiconductor devices, which may influence the overall performance of the final product.
The etching process for the 65 nm and 55 nm scale poly-silicon gate commonly comprises the following steps. Step 1: after growing poly-silicon composed of N-doped poly-silicon and undoped poly-silicon, forming a hard mask layer on the poly-silicon serving as an etching blocking layer and depositing an anti-reflection layer subsequently. Step 2: coating a photoresist and applying photolithography to form a patterned photoresist layer for the poly-silicon gate etching. Step 3: starting the etching process by etching the anti-reflection layer firstly using the patterned photoresist layer as a mask. Step 4: etching the hard mask layer. Step 5: removing the patterned photoresist layer in the etching machine. Step 6: etching the poly-silicon to from a poly-silicon gate. During the etching process for forming the poly-silicon gate, since the etching rate of the N-doped poly-silicon is larger than that of the undoped poly-silicon, a morphological difference will develop between them.